The invention relates to an electronic circuit that enables the detection of abnormal current leaks on a bit line of an electrically programmable read-only memory. It also relates to the associated method and to a memory circuit comprising a detection circuit such as this.
The invention is particularly designed to improve the testing of the memories when they come off the production line. The testing of the memories requires identification of the defective elements. The information is then used to determine whether or not the memory can be repaired. The repairing consists in activating the redundant elements of the circuit to replace the defective elements.
It can be seen that it is useful to be able to identify all the defective elements, firstly because the customer should be supplied with operational circuits and, secondly, because it is necessary to be sure that the circuit delivered to the customer is reliable and will not go out of order before its lifetime as guaranteed by the manufacturer.
Now, concerning more especially the bit lines of the electrically programmable read-only memories, it is possible that excessive current leaks on the bit lines may create difficulties.
It is recalled that the cells of such memories are organized in rows and columns, the cells of one and the same row having their gates connected together to a word line, and the cells of one and the same column having their drains connected to a bit line. All the sources of a same memory sector are connected together.
A word line decoder can be used to address a particular word line and to apply determined potentials depending on the mode of operation.
A bit line decoder can be used to select a particular bit line to connect it to a determined circuit element depending on the mode of operation.
A memory cell is addressed by the selection of a bit line and a word line.
In reading mode, the selection of a word line consists in taking this line to a reading potential of 5 volts for example. All the other word lines are taken to zero volts.
In reading mode, the selection of a bit line results in its connection to a reading amplifier by a current/voltage converter which delivers a voltage that corresponds to the current of the bit line.
The cell addressed in reading mode consumes or does not consume current on the bit line, depending on whether its state is blank or programmed. A corresponding potential is set up at output of the current/voltage converter. The reading is then done by comparison, in the reading amplifier of this potential, with that given by a reference circuit connected to a blank cell, the principle being that a blank cell is conductive at 5 volts and that a programmed cell is not conductive (or shows low conductivity)..sup.1 FNT .sup.1 See, e.g., the following U.S. patents, all of which are hereby incorporated by reference: U.S. Pat. No. 5,132,576, Sense amplifier having load device providing improved access time; U.S. Pat. No. 5,109,187, CMOS voltage reference; U.S. Pat. No. 4,965,473, Eprom low voltage sense amplifier; U.S. Pat. No. 4,908,795, Semiconductor integrated circuit device with built-in memories; U.S. Pat. No. 4,903,237, Differential sense amplifier circuit for high speed ROMS, and flash memory devices; U.S. Pat. No. 4,813,018, Nonvolatile semiconductor memory device; U.S. Pat. No. 4,807,188, Nonvolatile memory device with a high number of cycle programming endurance; U.S. Pat. No. 4,785,423, Current limited epld array; U.S. Pat. No. 4,783,764. Semiconductor integrated circuit device with built-in memories, and peripheral circuit which may be statically or dynamically operated; U.S. Pat. No. 4,775,958, Semiconductor memory system. These materials not only provide some indication of alternative approaches to sensing, but also provide some examples of the variety of integrated circuit contexts in which the innovation sense amplifier can be used.
In practice, if the potential is lower than that of the reference circuit, i.e. if the cell addressed consumes current, then the cell of the bit line is blank or erased. If it is greater, i.e. if the addressed cell consumes no current, then the cell is programmed. Now, if there are major current leaks on the bit line, it might be thought that the addressed cell is erased, whereas it will actually be programmed: the current leaks mask the real state of the cell.
These current leaks may be leaks at certain source-substrate junctions of the cells, due to a manufacturing defect. They may also come from an excessively depleted cell, a gate voltage at 0 volts being sufficient to turn on such a cell..sup.2 If a nonconducting cell is addressed on such a bit line, its programmed state may be masked by the erased state of an excessively depleted cell located on the same bit line. FNT .sup.2 This problem of depleted cells is encountered in electrically erasable memories. In these memories, an erasure voltage that is too high, and/or is applied for too long, will discharge the floating gate to an excessive degree and will deplete the cell.
In the invention, there is proposed an approach that does not modify the structure of the memory map. In the invention, it is desired to detect the defect in order to correct it if possible.
Hence, there is proposed a circuit for the detection of current leaks on the bit lines of a memory, said circuit being usable in tests in order to identify the bit lines having such a defect, in order to then repair them when this is possible.
The circuit for the detection of current leaks is an electronic circuit which enables the comparison of the current flowing through each of the bit lines of the memory map with a test current, when all the word lines are taken to zero volts. Indeed, under these conditions, the cells should not be conductive, for their conduction threshold is typically 2 to 2.5 volts for a blank cell and at least five volts for a programmed cell. However, if a cell is depleted, i.e. if its conduction threshold is negative or zero, or if there is a junction leak, a current is conducted by the bitline. This leakage current is compared with the test current. If this leakage current is greater than the test current, then the bit line could be filed as being defective.
The invention therefore relates to a circuit for the detection of leakage currents in a bit line of an electrically programmable read-only memory.
This circuit comprises chiefly a current generator and a control circuit for the application, in detection mode, of a control voltage to the current generator and for the activation of the ground connection of the gates of the cells of a bit line. A comparison circuit is used to detect a leakage current on a bit line greater than the current delivered by the current generator.